HLL-to-HDL Generation: Results and Challenges

This paper presents preliminary results of automated hardware generation from C code and discusses specific challenges. The research is part of a bigger project that aims to provide a semi-automatic tool platform for hardware-software co-design in the context of the reconfigurable computing systems. We present a case study involving the AES encryption algorithm. The automatically generated VHDL is compared to a manually crafted design. The generated design, as well as the manual one, are synthesized in Xilinx ISE 6.3i and the reported results are obtained from the actual execution on the MOLEN polymorphic processor. Even though the automatically generated VHDL does not contain any optimizations, speedup of 7 is observed. However, compared to manually tuned VHDL, there is still a difference of several orders of magnitude. This paper will explore the differences that explain the performance gap and identify sources of improvement and necessary optimizations that have to be implemented. Some of the considered optimizations regard parallelization of the execution, memory accesses and data location, optimal utilization of the available hardware resources (onchip memories, multipliers, etc), as well as identification of the most suitable computation model for a given algorithm. Keywords—HW-SW co-design, high-level synthesis, reconfigurable computing, HLL, HDL